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HI-518
Data Sheet June 1999 File Number
3147.2
8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer
The Hl-518 is a monolithic, dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual function of address input A2 enables the Hl-518 to be user programmed either as a single ended 8-Channel multiplexer by connecting `Out A' to `Out B' and using A2 as a digital address input, or as a 4-Channel differential multiplexer by connecting A2 to the Vsupply. The substrate leakages and parasitic capacitances are reduced substantially by using the Intersil Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (lD(OFF) < 100pA at 25oC) and fast settling (tSETTLE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control.
Features
* Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . 130ns * Settling Time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%) * Low Leakage (Typical) - IS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pA - ID(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15pA * Low Capacitance (Max) - CS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pF - CD(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pF * Off Isolation at 500kHz . . . . . . . . . . . . . . . . . 45dB (Min) * Low Charge Injection Error . . . . . . . . . . . . . . . . . . . 25mV * Single Ended to Differential Selectable (SDS) * Logic Level Selectable (LLS)
Applications
* Data Acquisition Systems * Precision Instrumentation
Ordering Information
PART NUMBER HI3-0518-5 HI1-0518-5 HI1-0518-8 TEMP. RANGE (oC) 0 to 75 0 to 75 -55 to 125 PACKAGE 18 Ld PDIP 18 Ld CERDIP 18 Ld CERDIP PKG. NO. E18.3 F18.3 F18.3
* Industrial Control
Pinout
HI-518 (CERDIP, PDIP) TOP VIEW
V+ 1 OUT B 2 IN8/4B 3 IN7/3B 4 IN6/2B 5 IN5/1B 6 GND 7 VDD/LLS 8 A2/SDS 9 18 OUT A 17 V16 IN4/4A 15 IN3/3A 14 IN2/2A 13 IN1/1A 12 ENABLE 11 A0 10 A1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HI-518 Truth Tables
TABLE 1. HI-518 USED AS AN 8-CHANNEL MULTIPLEXER OR DUAL 4-CHANNEL MULTIPLEXER (NOTE 1) USE A2 AS DIGITAL ADDRESS INPUT ENABLE L H H H H H H H H NOTE: 1. For 8-Channel single ended function, tie "Out A" to "Out B"; for dual 4-Channel function, use the A2 address pin to select between Mux A and Mux B, where Mux A is selected with A2 low. A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H ON CHANNEL TO OUT A None 1A 2A 3A 4A None None None None OUT B None None None None None 1B 2B 3B 4B TABLE 2. HI-518 USED AS A DIFFERENTIAL 4-CHANNEL MULTIPLEXER A2 CONNECTED TO V- SUPPLY ENABLE L H H H H A1 X L L H H A0 X L H L H ON CHANNEL TO OUT A None 1A 2A 3A 4A OUT B None 1B 2B 3B 4B
Functional Block Diagram
VDD /LLS
IN 1A N EN A0 A1 A2 Q A2 DECODER Q N P DECODER IN 4A P OUT A
IN 1B N P OUT B DECODER IN 4B N P
INPUT BUFFER AND DECODERS
MULTIPLEXER SWITCHES
A2 DECODE A2 H L VQ H L L Q L H L
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HI-518
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V Analog (VIN, VOUT) . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage: TTL Levels Selected (VDD/LLS Pin = GND or Open) VA0-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V VA2/SDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V CMOS Levels Selected (VDD /LLS Pin = VDD) VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V
Thermal Information
Thermal Resistance (Typical, Note 2). . . . JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package. . . . . . . . . . . . . . . . . 70 18 Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges HI-518-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-518-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) 25 Full 25 25 25 25 25 25 25 25 25 25 25 Full Full Full Full Full Full Full 25 Full 25 Full 25 Full 25 Full Full MIN 10 45 2.4 0.7VDD -14 -8 TYP 130 20 120 140 250 800 0.02 480 0.01 0.015 0.015 MAX 175 225 175 175 25 5 10 5 0.8 0.3VDD 1 20 +14 750 1,000 50 50 50 450 MIN 10 -5 TYP 130 20 120 140 250 800 0.02 480 0.01 0.015 0.015 MAX 175 225 175 175 25 5 10 5 0.8 0.3VDD 1 20 +15 750 1,000 50 50 50 540 UNITS ns ns ns ns ns ns ns mV dB pF pF pF pF V V V V A A V nA nA nA nA nA nA mW
PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Break-Before-Make Delay, tOPEN Enable Delay (ON), tON(EN) Enable Delay (OFF), tOFF(EN) Settling Time Charge Injection Error Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL (TTL) Input High Threshold, VAH (TTL) Input Low Threshold, VAL (CMOS) Input High Threshold, VAH (CMOS) Input Leakage Current, IAH (High) Input Leakage Current, IAL (Low) ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Off Input Leakage Current, lS(OFF) Off Output Leakage Current, ID(OFF) On Channel Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD
To 0.1% To 0.01% Note 6 Note 7
45 2.4 0.7VDD -15 -
Note 3 Note 3 Note 3 Note 3
Note 4 Note 5
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HI-518
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND (Note 3), Unless Otherwise Specified (Continued) TEST CONDITIONS VEN = 2.4V TEMP (oC) Full Full MIN -8 TYP MAX 15 15 MIN -5 TYP MAX 18 18 UNITS mA mA
PARAMETER I+, Current I-, Current NOTES:
3. VDD /LLS pin = open or grounded for TTL compatibility. VDD /LLS pin = VDD for CMOS compatibility. 4. At temperatures above 90oC, care must be taken to assure VIN remains at least 1.0V below the VSUPPLY for proper operation. 5. VIN = 10V, IOUT = -100A. 6. VIN = 0V, CL = 100pF, enable input pulse = 3V, f = 500kHz. 7. CL = 40pF, RL = 1K, VEN = 0.8V, VIN = 3VRMS , f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B exhibits 60dB of OFF isolation under the above test conditions.
Test Circuits and Waveforms
IOUT 100A
VDD /LLS = GND, Unless Otherwise Specified
EN V2 IN 10V OUT rON = V2 100A 10V OUT
0.8V
A ID(OFF) 10V OUT OUT EN EN 0.8V 10V 2.4V A2 A0 +15V V+ 3.5V ADDRESS DRIVE (VA) A2 /SDS 0V VA 50 A1 A0 OUTPUT 10% tA 2.4V -10V EN VDD/LLS GND -15V IN 8 OUTA OUTB V10 k 50 pF 10V IN 1 IN 2-7 10V
VIN
FIGURE 1. ON RESISTANCE TEST CIRCUIT
FIGURE 2. ID(OFF) TEST CIRCUIT (NOTE 8)
IS(OFF) A
A ID(ON)
10V
10V
10V
FIGURE 3. IS(OFF) TEST CIRCUIT (NOTE 8)
FIGURE 4. ID(ON) TEST CIRCUIT (NOTE 8)
50%
+10V
FIGURE 5A. MEASUREMENT POINTS FIGURE 5. ACCESS TIME NOTE:
FIGURE 5B. TEST CIRCUIT
8. Two measurements per channel: 10V and 10V. (Two measurements per device for ID(OFF) 10V and 10V.)
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HI-518 Test Circuits and Waveforms
VDD /LLS = GND, Unless Otherwise Specified (Continued)
+15V 3.5V V+ A2 /SDS IN 1 IN 2-7 VA OUTPUT S1 ON 50% 50% S8 ON 2.4V 50 A1 A0 EN VDD /LLS GND -15V IN 8 OUTA OUTB V800 VOUT 12.5pF +5V
ADDRESS DRIVE (VA) 0V
tOPEN
FIGURE 6A. MEASUREMENT POINTS FIGURE 6. BREAK-BEFORE-MAKE DELAY
FIGURE 6B. TEST CIRCUIT
+15V 3.5V V+ 50% 50% ENABLE DRIVE (VA) 0V A2 /SDS IN 1 +10V
90%
OUTPUT 10% 0V
A1 A0 50 EN VDD /LLS GND
IN 2-8
tON(EN) tOFF(EN)
VA
OUTA V-
800
12.5pF
-15V
FIGURE 7A. MEASUREMENT POINTS FIGURE 7. ENABLE DELAY
FIGURE 7B. TEST CIRCUIT
+15V 2.4V V+ 3V VA VOUT 0V VO EN IN A0 , A1 , A2 /SDS OUT A OR B
VOUT CL = 100pF
VA
GND
VDD /LLS
V-
-15V
FIGURE 8A. MEASUREMENT POINTS VO is the measured voltage error due to charge injection. The error in coulombs is Q = CL x VO . FIGURE 8. CHARGE INJECTION
FIGURE 8B. TEST CIRCUIT
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HI-518 Die Characteristics
DIE DIMENSIONS: 89 mils x 93 mils METALLIZATION: Type: AlCu Thickness: 16kA 2kA SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA 1.0kA Silox Thickness: 12kA 2.0kA WORST CASE CURRENT DENSITY: 1.43 x 105 A/cm2 TRANSISTOR COUNT: 356 PROCESS: CMOS-DI
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential.
Metallization Mask Layout
HI-518
EN A0 A1 A2/SDS VDD /LLS GND
IN 1/1A
IN 5/1B
IN 2/2A
IN 6/2B
IN 3/3A
IN 7/3B
IN 4/4A
IN 8/4B
V-
OUT A
V+
OUT B
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HI-518 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A)
18 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.960 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 24.38 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 18 0.200 0.070 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 18 5.08 1.78 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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HI-518 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 21.47 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 22.35 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.845 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.880 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 18 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 18
2.93
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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